I. Field of the Invention
This invention relates to solid state computer memory circuits and in particular to bipolar random access memories.
II. Background Information
Bipolar Random Access Memories (bipolar RAMs) are devices implemented in bipolar technology which store and recall information in binary form. The information can be stored or recalled in any order at the user's discretion (at random). Although conventional bipolar RAMs are widely used throughout the computer industry, the speed of operation is unacceptably slow for certain applications. This speed problem can be better appreciated through an understanding of the operation of a conventional bipolar RAM.
The basic element for data storage in a bipolar RAM is a memory cell, which is a bi-stable latch. Memory cells are physically placed in a rectangular array and connected by pairs of metal conductors called word lines and bit lines. A particular memory cell in the array is selected for data retrieval (a read operation) or data storage (a write operation) by selecting one particular pair of word lines and one particular pair of bit lines.
FIG. 1 shows a conventional bipolar RAM 10 which contains one memory cell 12. Memory cell 12 comprises two cross-coupled silicon controlled rectifiers (SCRs). An SCR is shown schematically as a PNP transistor and a dual emitter NPN transistor connected such that the base of the PNP is connected to the collector of the NPN and the base of the NPN is connected to the collector of the PNP. By cross-coupling the two SCRs (connecting the NPN collector and base nodes of one SCR correspondingly to the base and collector nodes of the other SCR) a bi-stable latch is constructed. The two stable states are represented by either one SCR or the other SCR conducting current.
Memory cell 12 has 4 external terminals and two internal nodes. The PNP emitters are connected together and to upper word line 18. Two NPN emitters from different SCRs are connected together and to lower word line 19. Two NPN emitters, one from each SCR are each connected to a bit line which together form a bit line pair 14 and 15. The internal memory cell nodes are nodes 16 and 17. Node 16 connects the base of NPN transistor 28' to the base of PNP transistor 29 and node 17 connects the base of NPN transistor 28 to the base of PNP transistor 29'.
Upper word line 18 is driven by an emitter follower (not shown). Connected to the lower word line 19 is a constant current sink which supplies current to memory cell 12 to maintain the bi-stable state of memory cell 12 when not selected. Memory cell 12 is selected by forcing a high voltage on upper word line 18 (selecting the row) and simultaneously turning on switchable current sinks 11 and 13 (selecting the bit line). When cell 12 is selected, read or write operations can be performed on memory cell 12.
Referring to memory cell 12, a "1" state can be defined when the voltage at node 17 is high and the voltage at node 16 is low. Correspondingly a "0" state is when the voltage at node 16 is high and the voltage at node 17 is low. During a read operation, memory cell 12 is selected and signals RD and RD are set to a read threshold voltage which is designed to be a voltage approximately midway between the voltages at the internal nodes 16 and 17 of the selected cell. In the read mode, if memory cell 12 is in the "1" state, node 17 is high (higher than RD) and the right side of memory cell 12 conducts current to current sink 13. Transistor 25 is off. Node 16 is low (lower than RD) and the left side of memory cell 12 is off. Transistor 24 conducts current to current sink 11. Since transistor 25 is off, only "keep alive" current is flowing through transistor 27.
Transistor 24 is on and its collector current plus a keep alive current is flowing through transistor 26. Transistor 26 is conducting more current than transistor 27 which creates a voltage difference at the collector nodes of transistors 26 and 27. This voltage difference indicates the state of selected memory cell 12 and is amplified and transmitted to the output to produce a logic "1" level corresponding to the state of selected memory cell 12. In a similar manner when the selected memory cell contains a "0" state, the corresponding logic "0" state will be transmitted to the output.
A write operation results in selected memory cell 12 being in a particular state corresponding to the data input. If selected memory cell 12, before writing, is in the opposite state of the input data, its state will be altered to correspond to the input data. If the state of selected memory cell 12, before writing, is already in the same state as the input data, its state will not be altered.
Referring to FIG. 1, a write "1" operation will be explained. Before a write operation, circuit 10 is in a read mode. In this mode both RD and RD are set to a read threshold voltage. To write a "1" to selected memory cell 12, voltage RD is lowered until its voltage is lower than the lowest of the two internal nodes 16 and 17. If node 17 is low (corresponding to "0" state) before the write operation, the right side of memory cell 12 will be off. When RD voltage is lowered, the voltage at bit line 15 will drop until memory cell 12 bit line emitter begins to conduct current to sink 13. This will cause the right side of memory cell 12 to turn on which will turn off the left side. In this manner the state of memory cell 12 is altered. When the voltage at node 16 is lower than the voltage at node 17 by sufficient margin, the write operation can be terminated and memory cell 12 will in time recover to the full differential voltage corresponding to the altered stable binary state. The write operation is terminated by raising voltage RD back to the read threshold voltage.
Write recovery time is defined as the time delay between the termination of the write signal, RD in this example, and the appearance of stable correct data at the output buffer. If memory cell 12 has not recovered such that node 17 voltage is higher than the read threshold voltage when the write operation is terminated, memory cell 12 will exhibit extended write recovery time. In this case two things will happen. First, when voltage RD is raised, the parasitic capacitance of bit line 15 will be charged through transistor 25 which will cause a transient current to flow through transistor 27 and to sense amplifier 22 that corresponds to the opposite state of the data written. Second, when voltage RD reaches the read threshold voltage, since the voltage at node 17 is still lower than the read threshold, transistor 25 will continue to conduct the current from current sink 13. In this case both transistors 24 and 25 are conducting and the voltage differential at sense amplifier 22 is small with an indeterminate polarity. Until memory cell 12 recovers (node 17 is higher than the read threshold) a correct stable state will not appear at the output. Once memory cell 12 recovers, the correct data will propagate to the output. In this manner the write recovery time will be a function of the time duration of the write pulse width in relation to the speed of writing into memory cell 12 including the speed of recovering to a readable level.
Memory cells which have slow writing characteristics such as the cross coupled SCR cell are frequently used because of their higher immunity to noise such as current transients caused by alpha particles. Although these cells exhibit reduced soft error rate they have the characteristic of longer write time and longer write recovery time.
It is therefore desirable to eliminate write recovery time and have correct, stable data available at the RAM output before the write and after the write is terminated, for all circuit conditions including the case when a short write time is used to write a slow writing memory cell.